Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 78
PG232 July 02, 2019 www.xilinx.com
Appendix A
Verification, Compliance, and
Interoperability
The MIPI CSI-2 RX Subsystem has been verified using both simulation and hardware testing.
A highly parameterizable transaction-based simulation test suite has been used to verify
the subsystem. The tests include:
• Different lane combinations and line rates
• High-Speed Data reception with short/long packets, different virtual channels and
different data types.
• All possible interleaving cases (data type and virtual channel)
• All possible output pixel, data type combinations.
• Recovery from error conditions
• Register read and write access
Hardware Validation
The MIPI CSI-2 RX Subsystem is tested in hardware for functionality, performance, and
reliability using Xilinx® evaluation platforms. The MIPI CSI-2 RX Subsystem verification test
suites for all possible modules are continuously being updated to increase test coverage
across the range of possible parameters for each individual module.
A series of MIPI CSI-2 RX Subsystem test scenarios are validated using the Xilinx
development boards listed in Tab le A -1. These boards permit the prototyping of system
designs where the MIPI CSI-2 RX Subsystem processes different short/long packets received
on serial lines.
Xilinx 7 series FPGA devices do not have a native MIPI IOB support. You will have to target
either the HR bank I/O or the HP bank I/O for the MIPI IP implementation. For more
Table A-1: Xilinx Development Board
Target Family Evaluation Board Characterization Board
Zynq® UltraScale+™ MPSoC ZCU102 N/A
Zynq 7000 ZC702 N/A
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Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English