MIPI CSI-2 RX Subsystem v4.0 13
PG232 July 02, 2019 www.xilinx.com
Chapter 1: Overview
Unsupported Features
• Some YUV Data Types (YUV 420 (8-bit and 10-bit)) are not supported when the Video
Format Bridge is included.
• Dynamic linerate is not supported.
• 8 lanes support is not included.
• Data scramble feature is not supported.
• Latency reduction and transport efficiency features are not supported.
Licensing and Ordering
License Checkers
If the IP requires a license key, the key must be verified. The Vivado® design tools have
several license checkpoints for gating licensed IP through the flow. If the license check
succeeds, the IP can continue generation. Otherwise, generation halts with error. License
checkpoints are enforced by the following tools:
• Vivado synthesis
• Vivado implementation
• write_bitstream (Tcl command)
IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does
not check IP license level.
License Type
This Xilinx module is provided under the terms of the Xilinx Core License Agreement. The
module is shipped as part of the Vivado® Design Suite. For full access to all core
functionalities in simulation and in hardware, you must purchase a license for the core.
Contact your local Xilinx sales representative for information about pricing and availability.
For more information, visit the MIPI CSI-2 RX Subsystem product web page.
Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual
Property page. For information on pricing and availability of other Xilinx LogiCORE IP
modules and tools, contact your local Xilinx sales representative.
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General