Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 14
PG232 July 02, 2019 www.xilinx.com
Chapter 2
Product Specification
Standards
• MIPI Alliance Standard for Camera Serial Interface CSI-2 v1.1 [Ref 1]
•MIPI Alliance Physical Layer Specifications, D-PHY Specification v1.1 [Ref 6]
• Processor Interface, AXI4-Lite: see the Vivado Design Suite: AXI Reference Guide
(UG1037) [Ref 7]
• Output Pixel Interface: see the AXI4-Stream Video IP and System Design Guide (UG934)
[Ref 2]
Performance
This section details the performance information for various core configurations.
Latency
The CSI2 RX Subsystem core latency is the time from the start-of-transmission (SoT) pattern
on the serial lines to the tvalid signal assertion at CSI-2 Rx Subsystem output. This includes
the D-PHY latency, MIPI RX Controller latency and VFB latency (if Video Format Bridge is
included in the Subsystem).
Figure 2-1 represents the latency calculation for the subsystem
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Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English