MIPI CSI-2 RX Subsystem v4.0 39
PG232 July 02, 2019 www.xilinx.com
Chapter 3: Designing with the Subsystem
Shared Logic in the Subsystem
Selecting Shared Logic in the Core implements the subsystem with the PLL inside the
subsystem to generate all the clocking requirement of the PHY layer.
Select Include Shared Logic in Core if:
• You do not require direct control over the PLL generated clocks
• You want to manage multiple customizations of the subsystem for multi-subsystem
designs
• This is the first MIPI CSI-2 RX Subsystem in a multi-subsystem system
These components are included in the subsystem, and their output ports are also provided
as subsystem outputs.
Shared Logic Outside Subsystem
The PLLs are outside this subsystem instance.
Select Include Shared Logic in example design if:
• This is not the first MIPI CSI-2 RX Subsystem instance in a multi-subsystem design that
shares PLLs generated from other MIPI CSI-2 RX Subsystem that is configured with
shared logic in the Core mode.
To fully utilize the PLL, customize one MIPI CSI-2 RX Subsystem with shared logic in the
subsystem and one with shared logic in the example design. You can connect the PLL
outputs from the first MIPI CSI-2 RX Subsystem to the second subsystem.
There should be at least one MIPI CSI-2 RX Subsystem with 'include shared Logic in the
Core' mode whose outputs for shared resources can be used in other MIPI CSI-2 RX
Subsystem generated with 'include shared logic in example design' mode.
Figure 3-3 shows the sharable resource connections from the MIPI CSI-2 RX Subsystem with
shared logic included (MIPI_CSI_SS_Master) to the instance of another MIPI CSI-2 RX
Subsystem without shared logic (MIPI_CSI_SS_Slave00 and MIPI_CSI_SS_Slave01) for
UltraScale+ devices.
To Next Page
Loading...
General