Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 38
PG232 July 02, 2019 www.xilinx.com
Chapter 3: Designing with the Subsystem
amount of HDL modifications required, but at the same time retains the flexibility of the
subsystem.
Shared logic in the CSI-2 RX Subsystem allows you to share PLLs with multiple instances of
the CSI-2 RX Subsystem within the same I/O bank.
There is a level of hierarchy called <component_name>_support. Figure 3-1 and Figure 3-2
show two hierarchies where the shared logic is either contained in the subsystem or in the
example design. In these figures, <component_name> is the name of the generated
subsystem. The difference between the two hierarchies is the boundary of the subsystem. It
is controlled using the Shared Logic option in the Vivado IDE Shared Logic tab for the MIPI
CSI-2 RX Subsystem. The shared logic comprises a PLL and some BUFGs (maximum of 4).
X-Ref Target - Figure 3-1
Figure 3-1: Shared Logic Included in the Subsystem
X-Ref Target - Figure 3-2
Figure 3-2: Shared Logic Outside the Subsystem
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Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English