Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 61
PG232 July 02, 2019 www.xilinx.com
Chapter 4: Design Flow Steps
Clock Placement
This section is not applicable for this subsystem.
Banking
The MIPI CSI-2 RX Subsystem MIPI D-PHY sub-core provides a Pin Assignment tab in the
Vivado IDE to select the HP I/O bank. The clock lane and data lane(s) are implemented on
the selected I/O bank BITSLICE(s).
Note:
This tab is not available for Xilinx 7 series FPGA device configurations.
Transceiver Placement
This section is not applicable for this subsystem.
I/O Standard and Placement
MIPI standard serial I/O ports should use MIPI_DPHY_DCI for the I/O standard in the XDC
file for UltraScale+ family. The LOC and I/O standards must be specified in the XDC file for
all input and output ports of the design. The MIPI CSI-2 RX Subsystem, MIPI D-PHY
sub-core generates the I/O pin LOC for the pins that are selected during IP customization.
No I/O pin LOC are provided for Xilinx 7 series FPGA designs.
You will have to manually select the clock capable I/O for Xilinx 7 series FPGA RX clock lane
and restrict the I/O selection within the I/O bank.
It is recommended to select the IO bank with VRP pin connected for UltraScale+ MIPI CSI-2
RX Subsystem configurations. If VRP pin is present in other I/O bank in the same I/O column
of the device the following DCI_CASCADE XDC constraint should be used. For example, I/O
bank 65 has a VPR pin and the D-PHY TX IP is using the IO bank 66.
set_property DCI_CASCADE {66} [get_iobanks 65]
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Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English