Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 24
PG232 July 02, 2019 www.xilinx.com
Chapter 2: Product Specification
Core Configuration Register
The Core Configuration register is described in Ta ble 2 - 8 and allows you to enable and
disable the MIPI CSI-2 RX Controller core and apply a soft reset during core operation.
0xDC
Image Information 2 for
VC15
Image information 2 of the current processing packet
with VC of 15
Notes:
1. Access type and reset value for all the reserved bits in the registers is read-only with value 0.
2. Register accesses should be word aligned and there is no support for a write strobe. WSTRB is not used internally.
3. Only the lower 7-bits (6:0) of the read and write address of the AXI4-Lite interface are decoded. This means that
accessing address 0x00 and 0x80 results in reading the same address of 0x00.
4. Reads and writes to addresses outside this table do not return an error.
Table 2-8: Core Configuration Register (0x00)
Bits Name Reset Value Access Description
31–2 Reserved N/A N/A Reserved
1 Soft Reset 0x0 R/W
1: Resets the core
0: Takes core out of soft reset
All registers reset to their default value (except for this
bit, Core Enable and Active lanes configuration).
In addition to resetting registers when this bit is set to 1:
• Shut down port is not asserted on the PPI lanes
• Internal FIFOs (PPI, Packet, Generic Short Packet) are
flushed
• Control Finite State Machine (FSM) stops processing
current packet. Any partially written packet to
memory is marked as errored. This packet, when
made available through the AXI4-Stream interface,
reports the error on TUSER[1].
0Core Enable0x1 R/W
1: Enables the core to receive and process packets
0: Disables the core for operation
When disabled:
• Shuts down port assertion on the PPI lanes
• Internal FIFOs (PPI, Packet, Generic Short Packet) are
flushed
• Control FSM stops processing current packet
Any partially written packet to memory is marked as
errored. This packet, when made available through
the AXI4-Stream interface, reports the error on
TUSER[1].
Notes:
1. The short packet and line buffer FIFO full conditions take a few clocks to reflect in the register clock domain from
the core clock domain due to Clock Domain Crossing (CDC) blocks.
Table 2-7: MIPI CSI-2 RX Controller Core Registers (Cont’d)
Address Offset Register Name Description
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Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English