Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 60
PG232 July 02, 2019 www.xilinx.com
Chapter 4: Design Flow Steps
Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9].
Constraining the Subsystem
This section contains information about constraining the subsystem in the Vivado Design
Suite.
Required Constraints
The XDC constraints are delivered when the subsystem is generated.
Device, Package, and Speed Grade Selections
The maximum possible line rate per lane is dependent on device selected.
For details about family/device specific line rate support refer UltraScale Architecture
SelectIO Resources User Guide (UG571)[Ref 16] . See the respective Xilinx 7 series FPGA
family device data sheet for details on the upper line rate limits.
Clock Frequencies
See Clocking.
Clock Management
The MIPI CSI-2 RX Subsystem generates the required clock constraints when generated
using out-of-context mode with <component_name>_fixed_ooc.xdc. You can use these or
update as required for other clock constraints.
Target Board C_EXDES_BOARD ZCU102
FMC Model C_EXDES_FMC
LI-IMX274MIPI-FMC V1.0 Single
Sensor
Design Topology C_EXDES_CONFIG MIPI_Video_Pipe_Camera_to_Display
TDATA Width AXIS_TDATA_WIDTH 32
TDEST Width AXIS_TDEST_WIDTH 4
TUSER Width (CSI-2 options) AXIS_TUSER_WIDTH 96
TUSER Width (VFB options) VFB_TU_WIDTH 1
Table 4-1: Vivado IDE Parameter to User Parameter Relationship (Cont’d)
Vivado IDE Parameter User Parameter Default Value
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Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English