MIPI CSI-2 RX Subsystem v4.0 55
PG232 July 02, 2019 www.xilinx.com
Chapter 4: Design Flow Steps
IODELAY_GROUP Name: This parameter is used to select the IODELAY_GROUP Name for
the IDELAYCTRL. All core instances in the same bank sharing IDELAYCTRL should have the
same name for this parameter. Select a unique name per bank.
Note:
Available only for 7 series configurations.
Enable 300 MHz clock for IDELAYCTRL: Select to enable external 300 MHz clock port.
Only available in AUTO calibration mode. This 300 MHz port is used for connecting to
IDELAYCTRL. When you disable this option, IDELAYCTRL uses 200 MHz clock
(dphy_clk_200M).
Embedded non-image Interface: Select to process and offload embedded non-image
CSI-2 packets (with data type code 0x12) using a separate AXI4-Stream interface. If
unselected, such packets are not processed and are ignored by the CSI-2 RX controller.
Filter User Defined data types: Select to Filter user defined data types (0x30 to 0x37) and
do not output on Image interface (unsupported ErrId ISR[8] will not be set even filtering is
enabled). If unselected, such packets are processed and presented on image interface.
Line Buffer Depth: Depth of internal RAM used to accommodate throttling on the output
video interface. Values are 128, 256, 512, 1024, 2048, 4096, 8192, or 16384.
Note:
There is no throttling allowed on the input to the PPI.
Pixels Per Clock: Select the number of pixels to output per clock on output interface.
Values are 1 (single pixel), 2 (dual pixel), or 4 (quad pixel).
TUSER Width: Width of the sideband signal [TUSER] to report information like the line
number, frame number, ECC, and CRC.
Allowed VC: Select the VC values to be used to while processing the packets. Values are All,
0, 1, 2, or 3.
Enable CRC: When set, CRC computation is performed on the packet payload and any
errors are reported.
Enable Active Lanes: When set, the core supports the dynamic configuration of the
number of active lanes from the maximum number of lanes selected during core generation
using the parameter Serial Data Lanes. For example, when Serial Data Lanes is set to 3, the
number of active lanes can be programmed using the protocol configuration register to be
1, 2, or 3. The core reports an error when the active lanes setting is greater than the serial
lanes setting through the interrupt status register, bit 21.
Shared Logic Tab
The Shared Logic tab page provides shared logic inclusion parameters. The subsystem
shared logic configuration screen is shown in Figure 4-3.
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