Xilinx Vivado MIPI CSI-2 - Page 56

MIPI CSI-2 RX Subsystem v4.0 56
PG232 July 02, 2019 www.xilinx.com
Chapter 4: Design Flow Steps
Shared Logic: Select whether the PLL are included in the core or in the example design.
Values are:
• Include Shared Logic in core
• Include Shared Logic in example design
X-Ref Target - Figure 4-3
Figure 4-3: Subsystem Customization Screen - Shared Logic
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