MIPI CSI-2 RX Subsystem v4.0 83
PG232 July 02, 2019 www.xilinx.com
Appendix B: Debugging
Hardware Debug
Hardware issues can range from link bring-up to problems seen after hours of testing. This
section provides debug steps for common issues. The Vivado debug feature is a valuable
resource to use in hardware debug. The signal names mentioned in the following individual
sections can be probed using the debug feature for debugging the specific problems.
General Checks
• Ensure MIPI DPHY and MIPI CSI-2 RX Controller cores are in the enable state by reading
the registers.
• Ensure Incorrect Lane Configuration is not set in the MIPI CSI-2 RX Controller Interrupt
Status register.
• Ensure line buffer full condition is not set in the MIPI CSI-2 RX Controller Interrupt
Status register. Core setting this bit implies that the input data rate is higher than the
output data rate. Consider either decreasing input data rate (DPHY Line rate) or
increase output data rate (Select appropriate output pixel per Clock: Single, Dual,
Quad).
• Ensure that the PULLUP constraints required for the AXI IIC core pins are set at the
system-level XDC when the AXI IIC core is enabled. (See the AXI IIC Bus Interface v2.0
LogiCORE IP Product Guide (PG090) [Ref 5] for more information).
• Following MIPI CSI-2 RX Controller registers can be monitored to confirm reception of
data packets
°
Packet count in Core Status register
°
Data type and Byte count in Image Information registers
°
Frame received bit in Interrupt Status register
• No packets received by MIPI CSI-2 Subsystem
°
Possible causes:
- No packets received at MIPI DPHY level itself
- Frame end packets not received or not passed the ECC checks at MIPI CSI-2 RX
Subsystem level
°
Debug instructions:
- Verify MIPI DPHY packet count registers. If the packet counts at MIPI DPHY level
are not getting reported, debug connections/paths from source to MIPI DPHY
Input
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General