MIPI CSI-2 RX Subsystem v4.0 42
PG232 July 02, 2019 www.xilinx.com
Chapter 3: Designing with the Subsystem
I/O Planning
The MIPI CSI-2 RX Subsystem provides an I/O planner feature for I/O selection. In the Pin
Assignment tab, dedicated byte clocks (DBC) or quad byte clocks (QBC) are listed for the
clock lane for the selected HP I/O bank. For the QBC clock lane, all of the I/O pins are listed
for data lane I/O selection but for the DBC clock lane only the byte group I/O pins are listed
for data lane I/O selection.
Eight MIPI CSI-2 RX Subsystem IP cores can be implemented per IO bank based on BITSLICE
and BITSLICE_CONTROL instances in the UltraScale+ devices.
IMPORTANT: If the RX data lane I/O pins are selected non-contiguously then an additional
one, two, or three I/O pins (RX_BITSLICE) are automatically used for clock/Strobe propagation.
Therefore, it is recommended that you select adjacent I/O pins for the RX configuration to
make efficient use of the I/O. The propagation of strobes to the RX data pins follows the
inter-byte and inter-nibble clocking rules given in the UltraScale Architecture SelectIO
Resources User Guide (UG571) [Ref 16]. All lanes of a particular MIPI CSI-2 RX Subsystem
instance need to be in the same HP IO bank which is automatically controlled by the Pin
Assignment tab of the XGUI for Ultrascale+ devices. Multiple MIPI CSI-2 RX Subsystem
instances sharing clocking resources also need to be in the same HP IO bank.
Figure 3-5 shows the eight MIPI CSI-2 RX Subsystem IP cores configured with one clock
lane and two data lanes and implemented in a single HP I/O bank.
The csi2_rx_master is configured with Include Shared Logic in core option and the
remaining cores are configured with Include Shared Logic in example design. The
constant clkoutphy signal is generated within the PLL of the csi2_rx_master core
irrespective of line rate and is shared with all other slave IP cores (csi2_rx_slave1 to
csi2_rx_slave7) with different line rates.
Note:
The master and slave cores can be configured with the different line rate when sharing
clkoutphy within IO bank.
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