EasyManuals Logo

Xilinx Vivado MIPI CSI-2 User Manual

Xilinx Vivado MIPI CSI-2
90 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #54 background imageLoading...
Page #54 background image
MIPI CSI-2 RX Subsystem v4.0 54
PG232 July 02, 2019 www.xilinx.com
Chapter 4: Design Flow Steps
Pixel Format: Select Data Type (pixel format) as per the CSI-2 protocol (RAW6, RAW7,
RAW8, RAW10, RAW12, RAW14, RGB888, RGB666, RGB565, RGB555, RGB444, YUV422_8bit).
Serial Data Lanes: Select the maximum number of D-PHY lanes for this subsystem instance.
Values are 1, 2, 3, or 4.
Enable AXI IIC: Select to add the AXI IIC core (for CCI support).
Include Video Format Bridge (VFB): Option to include or exclude the Video Format Bridge
core in the subsystem.
Support CSI Spec V2_0: Select to enable CSI V2.0 features (RAW16, RAW20 support and
VCX feature support).
Support VCX Feature: Option to include or exclude VCX feature.
Line Rate (Mb/s): Select the line rate for the MIPI D-PHY core. Value in the range, 80 to
2500 Mb/s based on the device selected. Vivado IDE automatically limits the line rates
based on the device selected. For details about family/device specific line rate support refer
UltraScale Architecture SelectIO Resources User Guide (UG571)[Ref 16]. See the respective 7
Series family device data sheet for details on the upper line rate limits.
D-PHY Register Interface: Select to enable the register interface for the MIPI D-PHY core.
Enable Deskew Detection: Select to enable Deskew sequence detection and centre
alignment of clock and data lanes in MIPI D-PHY.
Note:
Applicable only for line rates above 1500 Mb/s
Calibration Mode: Select the calibration for 7 Series MIPI D-PHY RX Subsystem. Values are
None, Fixed, or Auto. When set to None, the Calibration Mode does not add IDELAY2
primitive. Fixed as Calibration Mode will set IDELAYE2 TAP value set in IDELAY Tap Value.
Auto as Calibration Mode will add IDELAYE2 primitive and tap value will be configured by
D-PHY RX IP based on received traffic and calibration algorithm.
IDELAY Tap Value: Select the IDELAY TAP value used for calibration in Fixed mode. Value in
the range, 1 to 31.
Include IDELAYCTRL in core: Select to include IDELAYCTRL in core. Only available in FIXED
and AUTO calibration modes. For multiple MIPI CSI-2 Rx IP cores that are sharing single IO
bank, select Include IDELAYCTRL option in the IP for the auto calibration mode. Only one
IDELAYCTRL is available per a single clock region. If multiple MIPI CSI-2 RX cores exist in
single clock region, select this option for only one MIPI CSI-2 RX IP core. For the rest of MIPI
CSI-2 RX cores, this option should be unselected.
Note:
This option is applicable only for 7 Series MIPI CSI-2 RX IP configurations.
Send Feedback

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Xilinx Vivado MIPI CSI-2 and is the answer not in the manual?

Xilinx Vivado MIPI CSI-2 Specifications

General IconGeneral
BrandXilinx
ModelVivado MIPI CSI-2
CategoryReceiver
LanguageEnglish