Name: Xilinx ZCU106
Brand: Xilinx
Rating: 4 (1 reviews)

ZCU106 Board User Guide 129

UG1244 (v1.0) March 28, 2018 www.xilinx.com

Appendix B: Master Constraints File Listing

#USER_SI570 300 MHz

set_property PACKAGE_PIN AJ12 [get_ports "USER_SI570_N"] ;

set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_N"] ;

set_property PACKAGE_PIN AH12 [get_ports "USER_SI570_P"] ;

set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_P"] ;

#For completeness, the MGT clocks are documented here:

#MGTH 223 HDMI I/F

set_property PACKAGE_PIN AD7 [get_ports "HDMI_SI5324_OUT_C_N"]

set_property PACKAGE_PIN AD8 [get_ports "HDMI_SI5324_OUT_C_P"]

set_property PACKAGE_PIN AC9 [get_ports "HDMI_RX_CLK_C_N"] ;

set_property PACKAGE_PIN AC10 [get_ports "HDMI_RX_CLK_C_P"] ;

#MGTH 224 PCIE I/F

set_property PACKAGE_PIN AB7 [get_ports "PCIE_CLK_N"] ;

set_property PACKAGE_PIN AB8 [get_ports "PCIE_CLK_P"] ;

#MGTH 225 SDI, SMA_MGT, SFP0/1 I/F

set_property PACKAGE_PIN Y7 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"] ;

set_property PACKAGE_PIN Y8 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"] ;

set_property PACKAGE_PIN W9 [get_ports "SFP_SI5328_OUT_C_N"] ;

set_property PACKAGE_PIN W10 [get_ports "SFP_SI5328_OUT_C_P"] ;

#MGTH 226 HPC0 I/F

set_property PACKAGE_PIN V7 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"] ;

set_property PACKAGE_PIN V8 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"] ;

set_property PACKAGE_PIN U9 [get_ports "USER_MGT_SI570_CLOCK1_C_N"] ;

set_property PACKAGE_PIN U10 [get_ports "USER_MGT_SI570_CLOCK1_C_P"] ;

#MGTH 227 HPC0 I/F

set_property PACKAGE_PIN T7 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"] ;

set_property PACKAGE_PIN T8 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"] ;

set_property PACKAGE_PIN R9 [get_ports "USER_MGT_SI570_CLOCK2_C_N"] ;

set_property PACKAGE_PIN R10 [get_ports "USER_MGT_SI570_CLOCK2_C_P"] ;

#GTR 505 FIXED CLOCKS SOURCED FROM U69 SI5341B

#Other net PACKAGE_PIN P28 - GTR_REF_CLK_SATA_C_N Bank 505 - PS_MGTREFCLK1N_505

#Other net PACKAGE_PIN P27 - GTR_REF_CLK_SATA_C_P Bank 505 - PS_MGTREFCLK1P_505

#Other net PACKAGE_PIN M28 - GTR_REF_CLK_USB3_C_N Bank 505 - PS_MGTREFCLK2N_505

#Other net PACKAGE_PIN M27 - GTR_REF_CLK_USB3_C_P Bank 505 - PS_MGTREFCLK2P_505

#Other net PACKAGE_PIN M32 - GTR_REF_CLK_DP_C_N Bank 505 - PS_MGTREFCLK3N_505

#Other net PACKAGE_PIN M31 - GTR_REF_CLK_DP_C_P Bank 505 - PS_MGTREFCLK3P_505

#MEMORY

#DDR4 SODIMM J1 is a PS DDR Bank 504 Interface

#Other net PACKAGE_PIN AN34 - DR4_SODIMM_A0 Bank 504 - PS_DDR_A0

#Other net PACKAGE_PIN AM34 - DR4_SODIMM_A1 Bank 504 - PS_DDR_A1

#Other net PACKAGE_PIN AM33 - DR4_SODIMM_A2 Bank 504 - PS_DDR_A2

#Other net PACKAGE_PIN AL34 - DR4_SODIMM_A3 Bank 504 - PS_DDR_A3

#Other net PACKAGE_PIN AL33 - DR4_SODIMM_A4 Bank 504 - PS_DDR_A4

#Other net PACKAGE_PIN AK33 - DR4_SODIMM_A5 Bank 504 - PS_DDR_A5

#Other net PACKAGE_PIN AK30 - DR4_SODIMM_A6 Bank 504 - PS_DDR_A6

#Other net PACKAGE_PIN AJ30 - DR4_SODIMM_A7 Bank 504 - PS_DDR_A7

#Other net PACKAGE_PIN AJ31 - DR4_SODIMM_A8 Bank 504 - PS_DDR_A8

#Other net PACKAGE_PIN AH31 - DR4_SODIMM_A9 Bank 504 - PS_DDR_A9

#Other net PACKAGE_PIN AG31 - DR4_SODIMM_A10 Bank 504 - PS_DDR_A10

#Other net PACKAGE_PIN AF31 - DR4_SODIMM_A11 Bank 504 - PS_DDR_A11

#Other net PACKAGE_PIN AG30 - DR4_SODIMM_A12 Bank 504 - PS_DDR_A12

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English

Xilinx ZCU106 User Manual

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