Xilinx ZCU106 User Manual

ZCU106 Board User Guide 48
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
Clock Generation
The ZCU106 board provides fixed and variable clock sources for the XCZU7EV MPSoC.
Table 3-12 lists the source devices for each clock.
Table 3-13 lists the source devices for each clock.
Table 3-12: Clock Sources
Clock (Net) Name Frequency Clock Source
Fixed Frequency Clocks
PS_REF_CLK 33.33 MHz
U69 SI5341B clock generator
CLK_74_25 74.25 MHz
CLK_125 125 MHz
GTR_REF_CLK_SATA 125 MHz
GTR_REF_CLK_USB3 26 MHz
GTR_REF_CLK_DP 27 MHz
Programmable Frequency Clocks
USER_SI570 300 MHz (default) U42 SI570 I2C PROG. OSC.
USER_MGT_SI570 156.25 MHz (default) U56 SI570 I2C PROG. OSC.
USER_MGT_SMA User-Provided source J79 (P)/J80 (N) SMA CONN.
HDMI_SI5324_OUT Variable U108 SI5319C clock recovery
SFP_SI5328_OUT Variable U20 SI5328B clock recovery
Table 3-13: Clock Connections, Source to XCZU7EV MPSoC
Clock Source Ref.
Des. and Pin
Net Name I/O Standard XCZU7EV (U1) Pin
U69.59 PS_REF_CLK
(1)
R24
U69.45 CLK_125_P LVDS_25 H9
U69.44 CLK_125_N LVDS_25 G9
U69.51 CLK_74_25_P LVDS_25 D15
U69.50 CLK_74_25_N LVDS_25 D14
U69.35 GTR_REF_CLK_SATA_P
(2)
P27
U69.34 GTR_REF_CLK_SATA_N
(2)
P28
U69.31 GTR_REF_CLK_USB3_P
(2)
M27
U69.30 GTR_REF_CLK_USB3_N
(2)
M28
U69.24 GTR_REF_CLK_DP_P
(2)
M31
U69.23 GTR_REF_CLK_DP_N
(2)
M32
U42.4 USER_SI570_P DIFF_SSTL12 AH12
U42.5 USER_SI570_N DIFF_SSTL12 AJ12
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English