Xilinx ZCU106 User Manual

ZCU106 Board User Guide 85
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-34 lists the connections between the XCZU7EV MPSoC and the prototype header.
User I2C0 Receptacle
[Figure 2-1, callout 21]
The ZCU106 evaluation board supports a PMOD 2X6 receptacle (right-angle female) J160.
Figure 3-33 shows the I2C0 PMOD receptacle J160. The I2C0 nets are a branch of the I2C0
main bus (see Figure 3-17, page 61 and I2C0 (MIO 14-15), page 60 for more details).
Table 3-34: Prototype Header J3 Connections to the XCZU7EV MPSoC
XCZU7EV (U1) Pin Net Name I/O Standard Prototype Header J3 Pin
L14 L6P_AD6P_64_P LVCMOS18 8
K13 L6N_AD6N_64_N LVCMOS18 6
K14 L5P_AD14P_64_P LVCMOS18 12
J14 L5N_AD14N_64_N LVCMOS18 10
K12 L4P_AD7P_64_P LVCMOS18 16
J11 L4N_AD7N_64_N LVCMOS18 14
L12 L3P_AD15P_64_P LVCMOS18 20
L11 L3N_AD15N_64_N LVCMOS18 18
G23 L14P_HDGC_65_P LVCMOS18 24
G24 L14N_HDGC_65_N LVCMOS18 22
X-Ref Target - Figure 3-33
Figure 3-33: J160 PMOD I2C0 Right-Angle Receptacle
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English