Xilinx ZCU106 User Manual

ZCU106 Board User Guide 104
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
FPGA Mezzanine Card Interface
[Figure 2-1, callouts 32, 33]
The ZCU106 evaluation board supports the VITA 57.1 FPGA mezzanine card (FMC)
specification [Ref 23] by providing subset implementations of high pin count connectors at
J5 (HPC0) and J4 (HPC1). HPC connectors use a 10 x 40 form factor, populated with 400
pins. The connectors are keyed so that a mezzanine card, when installed in either of these
FMC connectors on the ZCU106 evaluation board, faces away from the board.
FMC HPC0 Connector J5
[Figure 2-1, callout 32]
The FMC connector at J5 (HPC0) implements a subset of the full FMC HPC connectivity:
• 68 single-ended, or 34 differential user-defined pairs (34 LA pairs: LA[00:33])
• Eight GTH transceiver DP differential pairs
• Two GBTCLK differential clocks
• 159 ground and 15 power connections
N29 PS_MGTRTXP3 GT3_SATA1_TX_P
(1)
2 HTX_P
SATA P9
N30 PS_MGTRTXN3 GT3_SATA1_TX_N
(1)
3 HTX_N
N33 PS_MGTRRXP3 GT3_SATA1_RX_P
(1)
6 HRX_P
N34 PS_MGTRRXN3 GT3_SATA1_RX_N
(1)
5 HRX_N
T27 PS_MGTREFCLK0P NC NA NA
NA
T28 PS_MGTREFCLK0N NC NA NA
P27 PS_MGTREFCLK1P GTR_REF_CLK_SATA_C_P
(1)
35 OUT3_P
SI5341B U69
P28 PS_MGTREFCLK1N GTR_REF_CLK_SATA_C_N
(1)
34 OUT3_N
M27 PS_MGTREFCLK2P GTR_REF_CLK_USB3_C_P
(1)
31 OUT2_P
M28 PS_MGTREFCLK2N GTR_REF_CLK_USB3_C_N
(1)
30 OUT2_N
M31 PS_MGTREFCLK3P GTR_REF_CLK_DP_C_P
(1)
24 OUT0_P
M32 PS_MGTREFCLK3N GTR_REF_CLK_DP_C_N
(1)
23 OUT0_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
Table 3-42: PS-GTR Bank 505 Interface Connections (Cont’d)
XCZU7EV
(U1) Pin
XCZU7EV Pin Name Schematic Net Name
(2)
Connected To
Pin No. Pin Name Device
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English