Xilinx ZCU106 User Manual

ZCU106 Board User Guide 37
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
The ZCU106 board DDR4 64-bit component memory interface adheres to the constraints
guidelines documented in the “PCB Guidelines for DDR4” section of UltraScale Architecture
PCB Design User Guide (UG583)[Ref 3]. The ZCU106 DDR4 component interface is a 40Ω
impedance implementations. Other memory interface details are also available in the
UltraScale Architecture FPGAs Memory Interface Solutions Product Guide (PG150) [Ref 4]. For
more details, see the Micron MT40A256M16GE-075E data sheet at the Micron website
[Ref 15].
PSMIO
Table 3-5 provides PS MIO peripheral mapping implemented on the ZCU106 board. See the
Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 2] for more information
on PS MIO peripheral mapping.
AF10 DDR4_ODT SSTL12_DCI K3 ODT U2,U99-U101
AD12 DDR4_CS_B SSTL12_DCI L7 CS_B U2,U99-U101
Table 3-4: DDR4 Component Memory Connection to the XCZU7EV MPSoC (Cont’d)
XCZU7EV
(U1) Pin
Net Name I/O Standard
DDR4 Component Memory
Pin # Pin Name Ref. Des.
Table 3-5: MIO Peripheral Mapping
MIO[0:25] Bank 500 MIO[26:51] Bank 501 MIO[52:77] Bank 502
0QSPI26PMU IN52USB0
1QSPI27DPAUX53USB0
2QSPI28DPAUX54USB0
3QSPI29DPAUX55USB0
4QSPI30DPAUX56USB0
5 QSPI 31 Not assigned/no connect 57 USB0
6 Not assigned/no connect 32 PMU OUT 58 USB0
7QSPI33PMU OUT59USB0
8QSPI34PMU OUT60USB0
9QSPI35PMU OUT61USB0
10 QSPI 36 PMU OUT 62 USB0
11 QSPI 37 PMU OUT 63 USB0
12 QSPI 38 GPIO 64 GEM3
13 GPIO 39 SD1 65 GEM3
14 I2C0 40 SD1 66 GEM3
15 I2C0 41 SD1 67 GEM3
16 I2C1 42 SD1 68 GEM3
17 I2C1 43 69 GEM3
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English