Xilinx ZCU106 User Manual

ZCU106 Board User Guide 54
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
GEM3 Ethernet (MIO 64-77)
[Figure 2-1, callout 12]
The PS-side Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet
interface (see Figure 3-12), which connects to a TI DP83867IRPAP Ethernet RGMII PHY
before being routed to an RJ45 Ethernet connector. The RGMII Ethernet PHY is boot
strapped to PHY address 5'b01100 (0x0C) and Auto Negotiation is set to Enable.
Communication with the device is covered in the DP83867 RGMII PHY data sheet [Ref 20].
10/100/1000 MHz Tri-Speed Ethernet PHY
[Figure 2-1, callout 12]
The ZCU106 board uses the TIDP83867IRPAP Ethernet RGMII PHY [Ref 20] (U98) for
Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII
mode only. The PHY connection to a user-provided Ethernet cable is through a Wurth
7499111221A RJ-45 connector (P12) with built-in magnetics.
The Ethernet connections from XCZU7EV MPSoC U1 to the DP83867IRPAP PHY device at
U98 are listed in Table 3-14.
X-Ref Target - Figure 3-12
Figure 3-12: Ethernet Block Diagram
Table 3-14: DP83867 PHY Connections to XCZU7EV MPSoC
XCZU7EV
(U1) Pin
Net Name
DP83867 PHY U98
Pin # Pin Name
J31 MIO64_ENET_TX_CLK 40 GTX_CLK
J32 MIO65_ENET_TX_D0 38 TX_DO
J34 MIO66_ENET_TX_D1 37 TX_D1
K28 MIO67_ENET_TX_D2 36 TX_D2
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0,2
5*0,,
0',2
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Xilinx ZCU106 Specifications

General

Brand	Xilinx
Model	ZCU106
Category	Motherboard
Language	English