Xilinx ZCU106 - Page 9

ZCU106 Board User Guide 9
UG1244 (v1.0) March 28, 2018 www.xilinx.com
Chapter 1: Introduction
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SFP+ (two GTH transceivers)
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FMC HPC0 DP (eight GTH transceivers)
• PL FMC HPC0 connectivity - full LA bus
• PL FMC HPC1 connectivity - partial LA bus
• PS MIO: dual Quad SPI
• PS MIO: two channels of quad-UART bridge
•PS MIO: CAN
• PS MIO: I2C shared across PS and PL
• PS MIO: SD
• PS MIO: DisplayPort
• PS MIO: system controller I/F
• PS MIO: Ethernet
•PS MIO: USB3
• PS-side user LED (one)
• PS-side user pushbutton (one)
• PL-side user LEDs (eight)
• PL-side user DIP switch (8-position)
• PL-side user pushbuttons (five)
• PL-side CPU reset pushbutton
•PL-side PMOD headers
• PL-side bank 0 PROG_B pushbutton
• Security - PSBATT button battery backup
• SYSMON (previously XADC), prototype header
• Operational switches (power on/off, PROG_B, boot mode DIP switch)
• Operational status LEDs (power status, INIT, DONE, PG, JTAG status, DDR power good)
• Power management
The ZCU106 provides designers a rapid prototyping platform using the
XCZU7EV-2FFVC1156 device. The ZU7EV contains many PS hard block peripherals exposed
through the multi-use I/O (MIO) interface and several FPGA programmable logic (PL),
high-density (HD), and high-performance (HP) banks. Table 1-1 lists a summary of the
resources available within the ZU7EV. A feature set overview, description, and ordering
information is provided in the Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891)
[Ref 1].
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