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Xilinx Zynq-7000 Design Guide

Xilinx Zynq-7000
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Zynq-7000 PCB Design Guide www.xilinx.com 3
UG933 (v1.8) November 7, 2014
12/04/2013 1.6
Changed “DDR3” to “DDR3/3L” throughout document. Updated capacitor quantities
and packages in Tab le 3- 1 and Ta ble 3-2 . Updated capacitor specifications in
Tabl e 3-3. Updated descriptions for V
CCPINT
– PS Internal Logic Supply and V
CCPAUX
PS Auxiliary Logic Supply. Deleted “Capacitor Consolidation Rules” section. Modified
next-to-last sentence under PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference
Voltage. Added paragraph preceding Ta bl e 5-5 and updated Table 5- 5. Updated Addr,
Command, Contrl output name in Figure 5-7. Deleted last sentence under DDR Trace
Length.
08/01/2014 1.7
Removed “and Pin Planning Guide” from title. Added recommendation to
Recommended PCB Capacitors per Device. Changed V
CCO
per Bank sub-heading from
“100 µF” to 47 µF” in Tabl e 3-1. Removed values for V
CCPLL
and replaced with
reference (Note 3) in Ta ble 3-2 . Changed “Terminal” type to “Terminal Tantalum” and
added “X7U” to 100 µF capacitor in Table 3-3. Modified first paragraph under Noise
Limits by removing specifications and adding a reference to the data sheet. Updated
second paragraph under Unconnected V
CCO
Pins. Changed Murata part number from
“GRM155R60J475ME47D” to “GRM155R60J474KE19” under Unconnected V
CCO
Pins.
Updated first paragraph under PS_DDR_VRN, PS_DDR_VRP – PS DDR Termination
Voltage. Updated Unused DDR Memory. Deleted last two sentences under PS_POR_B
– Power on Reset and last sentence under PS_SRST_B – External System Reset.
Changed “Boot Mode Pins” section (pins MIO[2] to MIO[8] to Boot Mode Pin MIO[8].
Modified Figure 5-5 (CKE resistor layout). Modified Figure 5-6 (changed clk signal to
differential signals CLK_P/CLK_N and added pull-down resistor to ODT). Added
separate column for DDR3L to Tab le 5-6 and modified values. Clarified DDR Trace
Length and DDR Trace Impedance sections. Clarified byte swapping under DDR
Routing Topology. Added last paragraph under Ethernet GEM. Deleted “Lower
Operating Frequencies (without Feedback Mode)” section from Chapter 6.
08/05/2014 1.7.1
Updated document to latest user guide template.
11/07/2014 1.8
Added XC7Z035 device to Tabl e 3-1 and Table 3-2. Added 10 µF capacitor to Tab le 3-3.
Updated Table 5-5 .
Date Version Revision
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Xilinx Zynq-7000 Specifications

General IconGeneral
SeriesZynq-7000
Number of CoresDual-core
Processor SpeedUp to 1 GHz
Device TypeSoC
Logic CellsUp to 350K
DSP SlicesUp to 900
External Memory InterfacesDDR3, DDR2, LPDDR2
I/O StandardsLVCMOS, HSTL, SSTL
Operating Temperature-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package OptionsVarious BGA packages
I/O Voltage3.3V

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