Zynq-7000 PCB Design Guide www.xilinx.com 68
UG933 (v1.8) November 7, 2014
Chapter 5: Processing System (PS) Power and Signaling
Equation 5-3
For Fmax1, TQSPICKOMAX and TQSPIDCK are the respective clock-to-out and setup times of
the Zynq-7000 AP SoC device. For Fmax2, Tckoflash and Tsuflash are the respective
clock-to-out and setup times of the flash device, and Tpd is the maximum PCB propagation
delay which includes Zynq device package propagation delay along with the flash package
propagation delay. (Zynq device propagation delays are available in the Vivado tools. See
flash vendor documentation for flash propagation delays). For Fmax3, Tholdflash is the
input hold time of the flash device, and TQSPICKOMIN is the minimum clock-to-out time of
the Zynq-7000 device.
Using data from DS191 and a popular flash vendor’s data sheet, the effect of trace delay on
the maximum frequency can be illustrated:
As can be seen from the table, Fmax3 is not dependent on trace delay as long as the clock
and data delays are equal. Fmax3 is only of concern with an unusually high hold time
requirement for the flash device. It is recommended to avoid flash devices with hold times
greater than 4.0 ns.
Fmax3
1
2 Thold
flash
TQSPICKOMIN–()×
---------------------------------------------------------------------------
=
TQSPICKO
min (ns)
TQSPICKO
max (ns)
TQSPIDCK
(ns)
Tckoflash
(ns)
Tsuflash
(ns)
Tholdflash
(ns)
Tpd (ns)
Fmax1
(MHz)
Fmax2
(MHz)
Fmax3
(Mhz)
Fmax
(MHz)
0.0 3.4 2.0 7.0 2.0 3.0 0.175 100 107 166 100
0.0 3.4 2.0 7.0 2.0 3.0
0.35 100 103 166 100
0.0 3.4 2.0 7.0 2.0 3.0
0.525 100 99 166 99
0.0 3.4 2.0 7.0 2.0 3.0
0.70 100 96 166 96
0.0 3.4 2.0 7.0 2.0 3.0
0.875 100 93 166 93
0.0 3.4 2.0 7.0 2.0 3.0
1.75 100 80 166 80
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