System Management
Basic System Configuration Guide 253
Transmission of a reference clock through a chain of Ethernet equipment requires that all
equipment supports Synchronous Ethernet. A single piece of equipment that is not capable of
performing Synchronous Ethernet breaks the chain. Ethernet frames will still get through but
downstream devices should not use the recovered line timing as it will not be traceable to an
acceptable stratum source.
Central Synchronization Sub-System
The timing subsystem for the platforms has a central clock located on the CPM
(motherboard). The timing subsystem performs many of the duties of the network element
clock as defined by Telcordia (GR-1244-CORE) and ITU-T G.781.
The system can select from up to three (7950 XRS) or four (7450 ESS and 7750 SR) timing
inputs to train the local oscillator. The priority order of these references must be specified.
This is a simple ordered list of inputs: {bits, ref1, ref2, ptp}. The CPM clock output shall have
the ability to drive the clocking for all line cards in the system. The routers support selection
of the node reference using Quality Level (QL) indications. See Figure 14 for a description
of the synchronization selection process for the CPM clock.
Figure 14: CPM Clock Synchronization Reference Selection
The recovered clock will be able to derive its timing from any of the following:
• OC3/STM1, OC12/STM4, OC48/STM16, OC192/STM64 ports (7450 ESS and
7750 SR only)
Note: Not all signals are available on all platforms.
al_0553
Qualifierref1
T1/E1,
SONET/SDH
SyncE
ACR
1588
T1/E1,
2048 kHz
T1/E1,
2048 kHz
ref2
ptp
BITSin
1
BITSin
2
Quality
Level [QL]
Quality Level
Override
Reference
Sector
Digital
Phase
Locked
Loop
(DPLL)
BITS
Output
Selector
Internal (Node)
Timing Reference
BITSout
T1/E1
2048 kHz
Qualifier
Quality
Level [QL]
Qualifier
Quality
Level [QL]
Qualifier
Quality
Level [QL]
Qualifier
Quality
Level [QL]
Mode 1) Priority
reference order
Mode 2) QL then
priority reference
order
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