System Management
Basic System Configuration Guide 255
7950 XRS-40 Extension Chassis Central Clocks
The central clock architecture described above applies to each chassis of the 7950 XRS-40.
There is a central clock located on each of the CPMs present in the extension chassis.
However, there is no configuration for the central clocks on the CPMs of the extension
chassis. The central clocks only use the BITS input ports of the extension chassis for their
input reference. It is assumed that the quality of the reference provided into the BITS input
ports of the extension chassis CPMs is equal to the quality of the Master chassis central
clocks. See the installation guide for appropriate physical cabling to support this architecture.
Synchronization Status Messages (SSM)
SSM provides a mechanism to allow the synchronization distribution network to both
determine the quality level of the clock sourcing a given synchronization trail and to allow a
network element to select the best of multiple input synchronization trails. Synchronization
Status messages have been defined for various transport protocols including SONET/SDH,
T1/E1, and Synchronous Ethernet, for interaction with office clocks, such as BITS or SSUs
and embedded network element clocks.
Table 30: Revertive, non-Revertive Timing Reference Switching Operation
Status of
Reference A
Status of
Reference B
Active Reference
Non-revertive Case
Active Reference
Revertive Case
OK OK A A
Failed OK B B
OK OK B A
OK Failed A A
OK OK A A
Failed Failed holdover holdover
OK Failed A A
Failed Failed holdover holdover
Failed OK B B
Failed Failed holdover holdover
OK OK A or B A
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