Network Synchronization
268 Basic System Configuration Guide
PTP Clock Synchronization
The IEEE 1588v2 standard allows for synchronization of the frequency and time from a
master clock to one or more slave clocks over a packet stream. This packet-based
synchronization can be over unicast UDP/IPv4 or multicast Ethernet.
As part of the basic synchronization timing computation, a number of event messages are
defined for synchronization messaging between the PTP slave port and PTP master port. A
one-step or two-step synchronization operation can be used, with the two-step operation
requiring a follow-up message after each synchronization message. Ordinary clock master
and boundary clock master ports use one-step operation; ordinary clock slave and boundary
clock slave ports can accept messages from either one-step or two-step operation master
ports.
The IEEE 1588v2 standard includes a mechanism to control the topology for synchronization
distribution. The Best Master Clock Algorithm (BMCA) defines the states for the PTP ports
on a clock. One port will be set into slave state and the other ports will be set to master (or
passive) states. Ports in slave state recovered synchronization delivered by from an external
PTP clock and ports in master state transmit synchronization to toward external PTP clocks.
The basic synchronization timing computation between the PTP slave and PTP master is
shown in Figure 18. This figure illustrates the offset of the slave clock referenced to the best
master signal during startup.
Figure 18: PTP Slave and Master Time Synchronization Computation
Master Slave
Sync
Follow_up (t1)
Delay_req
Delay_resp (t4)
38
40
42
44
46
48
50
52
54
56
58
60
62
40
42
44
46
48
50
52
54
56
58
60
62
64
O = Offset = Slave - Master
t1, t2, t3, t4 Are Measured Values
t2 - t1 = Delay + Offset = 51 - 44 = 7
t4 - t3 = Delay - Offset = 57 - 56 = 1
Delay = ((t2 - t1) + (t4 - t3))/2 = 4
Offset = ((t2 - t1) - (t4 - t3))/2 = 3
D = Delay
t1
t4
t2
OD
OSSG732
t3
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