Sequoia Series 181
7.3 Questionable Status Group
The Questionable Status registers record signals that indicate abnormal operation of the power source.
As shown in Figure 7-1, the group consists of the same type of registers as the Status Operation group.
Table 7-3: Questionable Status Register
The outputs of the Questionable Status group are logically-ORed into the QUEStionable summary bit
(3) of the Status Byte register.
7.4 Standard Event Status Group
This group consists of an Event register and an Enable register that are programmed by Common
commands. The Standard Event register latches events relating to the interface communication status
(see Figure 7-1). It is a read-only register that is cleared when read. The Standard Event Enable
register functions similarly to the enable registers of the Operation and Questionable status groups.
Command Action
*ESE programs specific bits in the Standard Event Enable register.
*ESR? reads and clears the Standard Event register.
The PON bit in the Standard Event register is set whenever the power source is turned on. The most
common use for PON is to generate an SRQ at power-on following an unexpected loss of power.
7.5 Status Byte Register
This register summarizes the information from all other status groups as defined in the IEEE 488.2
Standard Digital Interface for Programmable Instrumentation. The bit configuration is shown in Table
7-2.
Command Action
*STB? reads the data in the register but does not clear it (returns MSS in bit 6)
serial poll reads and clears the data in the register (returns RQS in bit 6)
The MSS Bit
This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service
Request Enable register. MSS is set whenever the power source has one or more reasons for
requesting service. *STB? reads the MSS in bit position 6 of the response but does not clear any of
the bits in the Status Byte register.
The RQS Bit
The RQS bit is a latched version of the MSS bit. Whenever the power source requests service, it sets
the SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller
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