ARM Cortex-A9 MBIST User Manual

Preface
ARM DDI 0414C Copyright © 2008 ARM Limited. All rights reserved. xv
Restricted Access Non-Confidential
Prefix B Denotes AXI write response channel signals.
Prefix C Denotes AXI low-power interface signals.
Prefix H Denotes Advanced High-performance Bus (AHB) signals.
Prefix P Denotes Advanced Peripheral Bus (APB) signals.
Prefix R Denotes AXI read data channel signals.
Prefix W Denotes AXI write data channel signals.
Further reading
This section lists publications by ARM and by third parties.
See
http://infocenter.arm.com for access to ARM documentation.
ARM publications
This book contains information that is specific to this product. See the following
documents for other relevant information:
• Cortex-A9 Technical Reference Manual (ARM DDI 0388)
• Cortex-A9 Configuration and Sign-Off Guide (ARM DII 0146)
• AMBA AXI Protocol Specification (ARM IHI 0022)
• ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
(ARM DDI 0406).

ARM Cortex-A9 MBIST Specifications

General

Architecture	ARMv7-A
Clock Speed	Up to 2 GHz
Memory Management Unit	Yes
TrustZone	Yes
Core Count	1-4
Instruction Set	ARM, Thumb-2
Pipeline	8-stage
Floating Point Unit	VFPv3
NEON	Optional
L1 Cache	32KB Instruction, 32KB Data, per core
MBIST	Built-in Memory BIST