155
2467S–AVR–07/09
ATmega128
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
Timer/Counter
Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T2
) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set. Figure 68 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 68. Timer/Counter Timing Diagram, no Prescaling
Figure 69 shows the same timing data, but with the prescaler enabled.
Figure 69. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 70 shows the setting of OCF2 in all modes except CTC mode.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
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