Atmel ATmega128

269
2467S–AVR–07/09
ATmega128
103 RSTT Reset Logic
(Observe-only)
102 RSTHV
101 EXTCLKEN Enable signals for main Clock/Oscillators
100 OSCON
99 RCOSCEN
98 OSC32EN
97 EXTCLK (XTAL1) Clock input and Oscillators for the main clock
(Observe-only)
96 OSCCK
95 RCCK
94 OSC32CK
93 TWIEN TWI
92 PD0.Data Port D
91 PD0.Control
90 PD0.Pullup_Enable
89 PD1.Data
88 PD1.Control
87 PD1.Pullup_Enable
86 PD2.Data
85 PD2.Control
84 PD2.Pullup_Enable
83 PD3.Data
82 PD3.Control
81 PD3.Pullup_Enable
80 PD4.Data
79 PD4.Control
78 PD4.Pullup_Enable
77 PD5.Data
76 PD5.Control
75 PD5.Pullup_Enable
74 PD6.Data
73 PD6.Control
72 PD6.Pullup_Enable
71 PD7.Data
70 PD7.Control
69 PD7.Pullup_Enable
68 PG0.Data Port G
Table 106. ATmega128 Boundary-scan Order (Continued)
Bit Number Signal Name Module