329
2467S–AVR–07/09
ATmega128
Table 139. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 16 MHz
10 t
RLDV
Read Low to Data Valid 325 3.0t
CLCL
-50 ns
12 t
RLRH
RD Pulse Width 365 3.0t
CLCL
-10 ns
15 t
DVWH
Data Valid to WR High 375 3.0t
CLCL
ns
16 t
WLWH
WR Pulse Width 365 3.0t
CLCL
-10 ns
Table 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 16 MHz
10 t
RLDV
Read Low to Data Valid 325 3.0t
CLCL
-50 ns
12 t
RLRH
RD Pulse Width 365 3.0t
CLCL
-10 ns
14 t
WHDX
Data Hold After WR High 240 2.0t
CLCL
-10 ns
15 t
DVWH
Data Valid to WR High 375 3.0t
CLCL
ns
16 t
WLWH
WR Pulse Width 365 3.0t
CLCL
-10 ns
Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state
Symbol Parameter
4 MHz Oscillator Variable Oscillator
UnitMin Max Min Max
01/t
CLCL
Oscillator Frequency 0.0 8 MHz
1t
LHLL
ALE Pulse Width 235 t
CLCL
-15 ns
2t
AVLL
Address Valid A to ALE Low 115 0.5t
CLCL
-10
(1)
ns
3a t
LLAX_ST
Address Hold After ALE Low,
write access
55
ns
3b t
LLAX_LD
Address Hold after ALE Low,
read access
55
ns
4t
AVLLC
Address Valid C to ALE Low 115 0.5t
CLCL
-10
(1)
ns
5t
AVRL
Address Valid to RD Low 235 1.0t
CLCL
-15 ns
6t
AVWL
Address Valid to WR Low 235 1.0t
CLCL
-15 ns
7t
LLWL
ALE Low to WR Low 115 130 0.5t
CLCL
-10
(2)
0.5t
CLCL
+5
(2)
ns
8t
LLRL
ALE Low to RD Low 115 130 0.5t
CLCL
-10
(2)
0.5t
CLCL
+5
(2)
ns
9t
DVRH
Data Setup to RD High 45 45 ns
10 t
RLDV
Read Low to Data Valid 190 1.0t
CLCL
-60 ns
11 t
RHDX
Data Hold After RD High 0 0 ns