Atmel ATmega128

331
2467S–AVR–07/09
ATmega128
Figure 157. External Memory Timing (SRWn1 = 0, SRWn0 = 0
Figure 158. External Memory Timing (SRWn1 = 0, SRWn0 = 1)
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8
AddressPrev. addr.
DA7:0
Address
Data
Prev. data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4