Cisco ONS 15454 - Figure 5-7 ML100 T-12 Faceplate and Block Diagram; ML100 T-12 Card-Level Indicators

5-20
Cisco ONS 15454 Reference Manual, R7.0.1
OL-9217-01
Chapter 5 Ethernet Cards
5.8 5.8.1 ML100T-12 Card-Level Indicators
Figure 5-7 ML100T-12 Faceplate and Block Diagram
The card features two virtual packet over SONET (POS) ports with a maximum combined bandwidth of
STS-48. The ports function in a manner similar to OC-N card ports, and each port carries an STS circuit
with a size of STS-1, STS-3c, STS-6c, STS-9c, STS-12c, or STS-24c. To configure an ML-Series card
SONET STS circuit, refer to the “Create Circuits and VT Tunnels” chapter of the
Cisco ONS 15454 Procedure Guide.
The ML-Series POS ports supports virtual concatenation (VCAT) of SONET circuits and a software link
capacity adjustment scheme (SW-LCAS). The ML-Series card supports a maximum of two VCAT
groups with each group corresponding to one of the POS ports. Each VCAT group must be provisioned
with two circuit members. An ML-Series card supports STS-1c-2v, STS-3c-2v and STS-12c-2v. To
configure an ML-Series card SONET VCAT circuit, refer to the “Create Circuits and VT Tunnels”
chapter of the Cisco ONS 15454 Procedure Guide.
5.8.1 ML100T-12 Card-Level Indicators
The ML00T-12 card supports two card-level LED indicators. The card-level indicators are described in
Table 5-15.
1
2
3
4
5
6
7
8
9
10
11
ACT
FAIL
ML100T
12
134621
0
DOS
FPGA
BTC192
port
1
4xMag.
12 x
RJ45
Octal
PHY
port
0
SMII RGGI
Octal
PHY
4xMag.
4xMag.
4
6
port
A
port
B
port
3
port
2
port
0
port
1
ch0-1 ch4-5
6
RGGI
SCL
B
a
c
k
p
l
a
n
e
BPIA
Main
Rx
BPIA
Protect
Rx
BPIA
Main
Tx
BPIA
Protect
Tx
Processor
Daughter Card
128MB SDRAM
16MB FLASH
8KB NVRAM
Packet
Buffer
6MB
Packet
Buffer
6MB
Packet
Buffer
4MB
4
2
2
4
4
2
2
Control Mem
2MB
Control Mem
2MB
Result Mem
2MB