GE PACSystems RX7i

Chapter 6. Service Request Function
332 PACSystems* RX7i, RX3i and RSTi-EP CPU Programmer's Reference Manual GFK-2950C
6.32.5 Parameter Block
Address+0
Memory type. Refer to Memory Type Codes below.
Address+1
The zero-based offset N to read from nonvolatile storage. Contains the complete offset for any
memory area except %W, which also requires the use of address + 2 for offsets greater
than 65,535.
▪ For %I, %Q, %M, %T, and %G memory in byte mode, N = (Ra - 1) / 8, where Ra = one-based
reference address. For example, to read from the one-based bit reference address %T33,
enter the byte offset 4: (33 - 1) / 8 = 4.
▪ For %W, %R, %AI, and %AQ memory, and for %I, %Q, %M, %T, and %G memory in bit mode,
N = Ra - 1. For example, to read from the one-based reference address %R200, enter the
zero-based reference offset 199; to read from %I73 in bit mode, enter offset 72. For
memory in bit mode, the offset must be set on a byte boundary, that is, a number exactly
divisible by 8: 0, 8, 16, 24, and so on.
Address+2
Address+3
Length. The number of items to read from nonvolatile storage beginning at the reference
address calculated from the offset defined at [address + 1 and address + 2]. The length can be
one of the following:
Description
Valid range
The number of words (16-bit registers) to read
from %W, %R, %AI, or %AQ nonvolatile storage
1 through 32 words
The number of bytes to read from %I, %Q, %M,
%T, or %G in byte mode nonvolatile storage
1 through 64 bytes
The number of bits to read from %I, %Q, %M, %T,
or %G in bit mode nonvolatile storage
1 through 512 bits in
increments of 8 bits
The value must reside in the low byte of address + 3. The high byte must be set to zero.
Address + 4
Destination memory. The CPU memory area to write the read data to. This does not need to be
the same memory area as specified at [address]. Writing to a different memory area enables
you to compare the values that were already in the CPU with the values read from nonvolatile
storage.
Address+5
The zero-based offset N in CPU memory to start writing the read data to. Address + 5, the least
significant word, contains the complete offset for any memory area except %W, which also
requires the use of address + 6 for offsets greater than 65,535.
▪ For %I, %Q, %M, %T, and %G memory in byte mode, N = (Ra - 1) / 8, where Ra = one-based
reference address. For example, to write to the one-based bit reference address %T33,
enter the byte offset 4: (33 - 1) / 8 = 4.
▪ For %W, %R, %AI, and %AQ memory, and for %I, %Q, %M, %T, and %G memory in bit mode,
N = Ra - 1. For example, to write to the one-based reference address %R200, enter the
zero-based reference offset 199; to write to %I73 in bit mode, enter offset 72.
Address+6
Address+7
▪ When bit 0 is set to 1, storage disabled conditions are ignored. A read is allowed even if the
logic in RAM has changed since nonvolatile storage was read or written.
▪ Bits 1 through 15 must be set to zero; otherwise, the read fails.
Address+8
Reserved. Must be set to zero; otherwise, the read fails.
Address+9
Response status. The status read from nonvolatile storage. The low byte contains the major
error code; the high byte contains the minor error code.
For definitions, refer to Response Status Codes for SVC_REQ 56.
Address+10
Response Count. The number of words, bytes, or bits copied.