Hioki 3237 - Standard Event Registers

58
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7.2 Communication
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bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
Standard event status re
g
isters
(
SESR
)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
Standard event status enable re
g
isters
(
SESER
)
＆
Logical
sum
＆
＆ ＆
＆＆＆
＆
bit5
ESB
bit6
RQS
MSS
Standard Event Registers
(1) Standard event status register (SESR)
The standard event status register is an 8-bit register. If any bit in the
standard event status register is set to 1 (after masking by the standard event
status enable register), bit 5 (ESB) of the status byte register is set to 1.
The standard event status register is cleared in the following four situations:
① When a ∗CLS command is received.
② When an ∗ESR? query is received.
③ When the unit is powered on.
④ When the I/F is Switched.