Portable
PLUS
Computer
Functional
Description
5-3
5.2
Central Processing Unit (CPU)
The CPU (A2U1) is a CMOS 16-bit 80C86 microprocessor which performs three primary functions:
• Controls the operation of circuits according to programs
and
data stored in system RAM/ROM,
mass storage
RAM,
and the configuration EPROM.
•
Directs the transfer of data
on
the CPU address/data bus
and
on the data bus.
• Responds to interrupts from the PPU
and
keyboard interface circuits.
The
CPU operates at 5.33 MHz using a clock signal
(CLK)
provided by the clock/ready circuit (de-
scribed in section 5.14).
The
CPU communicates via a multiplexed 16-line address/data bus (ADO-AD15). These lines carry
address information
and
data during separate portions of the bus cycle. Four additional address lines
(A16-A19) provide the
CPU with
20
address lines in all. Output line
M/IO*
selects either 20-bit
addresses in main memory or 16-bit addresses in
I/O
memory. The only devices
on
this bus are
the
LCD
controller (A2U10), a buffer (A2U8) providing the interrupt acknowledge vector, three address
latches
(A2U3, A2U4, and A2U5), and a pair of data bus transceivers (A2U11,
and
A2U12). The
latches create a latched address bus and the transceivers create a data bus. The address
and
data buses
connect to all internal devices
and
to the two plug-in ports.
The
CPU is strapped into minimum mode and produces its own bus control signals. Non-maskable
interrupts (NMI) can't occur because the NMI pin is grounded. A wait instruction will act as a
NOP
because the TEST* pin is grounded. During interrupt cycles, buffer (A2U8) always provides
the
CPU
with a vector
of
FF
hex.
(Software must poll to determine which device caused the interrupt.) The two
data bus transceivers do not turn on during interrupt acknowledge cycles, so
an
addressed plug-in
card is free to drive its data bus at these times.
Power
is
removed from the CPU during the sleep state. When power is applied
at
power-up,
the
CPU
initializes itself internally.
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