HP Portable PLUS - Miscellaneous LCD Negative Supply Circuitry

Portable PLUS Computer
Functional Description 5-21
During tall, the comparator output is low. This means that A2Q72 and A2Q73 are off. The voltage at
the comparator '-' input is VREF (A2Q74 is on). Assume that the voltage across A2R105 is zero, so
the voltage at the
.+' input of the comparator is equal to the voltage at A2C60. Since the comparator
output is low, the .+' input voltage must be lower than the "-' input voltage. With A2Q72 off, the
voltage
at the node common to A2R102, A2R103, and A2R104 is more than VREF, and A2C60 is
charged through A2R104. When the voltage at A2C60 climbs just above VREF, the comparator output
switches high, and toff begins.
During
toff, A2Q73 is turned on. This pulls down the voltage at the '-' input of the comparator to
I/2VREF. A2Q72 is also turned on, so the voltage at the node common to A2R102, A2R103, and
A2R104 is less than 1/ 2 VREF. This discharges A2C60 through A2R104. When the voltage at A2C60
falls below I/2VREF, toff ends and tall begins again.
Thus,
tall is the time that it takes A2C60 to be charged from 1!2 VREF to VREF. toff is the discharge time
of A2C60 from VREF to I/2VREF. Since A2R103 is small in comparison with the other resistors in the
circuit,
toff is relatively constant. It ;.s determined predominately by A2R104 and A2C60. tall is the key
parameter
that is varied to control the voltage at VFETBIAS . When STEP8 through STEP1 are set to
logic 1 (open circuit), maximum charge current
is supplied to charge A2C60 during tall, so tall is at its
minimum for a given
VBAT. This makes VFETBIAS at its minimum magnitude, -8Y. When STEP8
through STEP1 are set to logic 0 (ground), charge current is shunted away from A2C60. The net
charge current for
A2C60 is at a minimum for a given VBAT, so /011 is at a maximum. This makes
VFETBIAS
at its maximum magnitude of -13 V. The 14 voltage levels of VFETBIAS between these
two extremes are achieved by varying the charge current
shunted away from A2C60 through A2R97,
A2R98, A2R99,
and A2RlOO.
For a given state of STEP8 through STEP1, VFETBIAS remains constant as VBAT varies. Since
VFETBIAS
is given by - VBAT x (tOIl/tOjf), as VBAT increases, tall decreases to keep VFETBIAS con-
stant. This is accomplished by sourcing the A2C60 charge current from VBAT through A2RlOl. As
VBAT increases, the charge current increases, which makes tall decrease.
5.15.9 Miscellaneous LCD Negative Supply Circuitry
A2C61 provides positive feedback for the A2U52 oscillator, which prevents spurious high-frequency
oscillation at the switch times
of the output . When the output switches, A2C61 couples the transition
back to the
.+' input, and A2R105 allows it to decay to the A2C60 voltage.
When SLEEP is at logic 0 (awake mode), power is provided to the A2U52 oscillator through A2Q71
from
VBAT. SLEEP at logic 0 turns off A2Q87. This allows VccS to pull up the gate voltage of A2Q82,
turning A2Q82 on. A2Q82 in
turn allows current to flow through A2R108, pins 1 and 2, and the base
of A2Q71, turning
on A2Q71.
When SLEEP is driven to logic 1 (sleep mode), A2Q87 turns on, turning off A2Q82. The base current
to A2Q71
is interrupted and A2R108, pins 3 and 4. This ensures that A2Q71 stays off. Power to
A2U52 is interrupted, although its open collector output at pin 7 is held at VBAT.
A2Q74 is turned on and off along with A2Q82. When on in awake mode, it passes VREF to the
A2U52 oscillator. A2Q74 turns off in sleep mode so that, when not operating, the A2U52 oscillator
circuit does not load
VREF.