5-18
Functional
Description
Portable
PLUS
Computer
The PPU takes
an
active part in the charge cycle of the battery.
It
uses the fuel gauge variable in the
execution of this contol. When a recharger
is
plugged in and the fuel gauge
is
less than 100%, the PPU
sets
FLOAT
to logic 0, which causes the battery charger regulator to try to regulate at overcharge
voltage.
If
the battery
is
low, the recharger
is
not be able to provide enough current for the regulator
to develop overcharge voltage across the battery. The HlGHCURRENT* output will be at logic
0,
since the regulator will be supplying its maximum current. Every 30 seconds, the PPU sets
FLOAT
to
logic 1 for
lis
second. This causes the battery charger regulator to try to regulate at float voltage (lower
than overcharge voltage) during this period. The
PPU then samples the HIGHCURRENT*
output
from the battery charger circuit.
If
HIGHCURRENT*
is
still at logic 0 during the lis-second interval,
then the
PPU continues updating the fuel gauge as described above, using a value of 280 rnA for the
charger current. As the charge cycle progresses, the battery voltage gradually increases.
If
during the lis-second interval the PPU reads HIGHCURRENT* as a high impedance, then the bat-
tery voltage has reached the float voltage level. This means that the battery
is
about 80% charged.
If
the fuel gauge value
is
less than 80%, the PPU sets it to 80%. For the rest of the charge cycle, the PPU
uses 250 rnA for charger current in the updating of the fuel gauge.
When the fuel gauge finally reaches
100% (or 4 hours later, whichever comes first), the PPU sets
FLOAT
to logic 1
and
holds it there as long as the recharger
is
connected. In the updating of the fuel
gauge, the
PPU uses a value for charger current which
is
equal to the load current, so the fuel gauge
stays at
100%. Once 100% charged, the battery charger maintains the battery voltage at the float
voltage, which maximizes battery life and keeps it fully charged.
5.1
5.4
Power-Up Routine
The following list describes the power-up sequence shown in figure 5-3.
1.
When the computer
is
in sleep mode, VccDS
is
3.25V nominal,
VccS
is
floating, and SLEEP*
is
at
ov.
When the reset
button
is
pressed, the PPU is reset
and
all its outputs are tristated.
2.
When the reset button
is
released,
PWON*
rises to VccDS in 700
to
800 ms. The PPU begins
running as the logic 1 threshold of its
"reset" input is reached. Then the PPU waits about 1.5
seconds for
PWON*
to reach the VccDS voltage level. (This provides noise immunity
on
the
slow-rising
PWON*
.)
3.
The PPU
now
initializes its pins to the following states:
SLEEP*
OV
DSLEEP VccDS
LCDON*
VccDS
RS-2320N
OV
SLEEP
VccDS
MODEMON
OV
4.
The PPU checks various internal variables.
If
they are invalid,
it
assumes that true "power on"
occurred, waits until
both
cards are plugged-in
alld
the
<ID
(contrast) key pressed,
and
then
pro-
ceeds to step 5.
If
the variables are valid, the PPU assumes that the reset
button
has
been pressed,
and
then
waits
until
both
cards are plugged-in before proceeding to step 5.
(You
don't
need to press the
<ID
(contrast) key in this case.)
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