5·12 Functional Description
Portable PLUS Computer
The Demodulator.
The demodulator circuit consists of the demodulator
IC
(A3U2), the base-band
sine/FSK filter
(A3U6A/B/C,
A3USA, A3U7 A/B, A3C4-A3C7,
and
A3R2),
and
the
base-band cosine
filter (A3UA/B, A3USB, A3C1-A3C3,
and
A3R1). Working together, these circuits recover the modu-
lated data
and
provide
both
the receive data
(RCVDATA)
and
a receive data clock RCVCLK (A3U2,
pins 3
and
2)
to the modulator IC (A3U3, pins 7
and
8).
Note that all transmitted
and
received data passes through
the
modulator
IC
on their way to or from
the computer's motherboard PCA.
The Base·Band Sine/FSK Filter. This filter switches between DPSK mode
and
FSK
mode via A3U6A,
A3U6B,
and
A3U6C. In
FSK
mode, it performs the
FSK
demodulation. In DPSK mode, it filters
out
the
sine component of the signal.
The
demodulator
IC
then combines this sine component with the cosine
component to do the DPSK demodulation.
The Base·Band Cosine Filter. This filter is only used to isolate the cosine component
of
the received
data
signal. The demodulator
IC
combines this with the sine component to determine
the
phase
shift
of
the
receive data signal,
and
thus be able to demodulate the DPSK signals.
The Phone Line Interface. The
phone
interface is designed to meet all the FCC
and
Canadian
DOC
regulations governing direct-connect modems. The "hook-switch' A3U17 controls
whether
the
phone
is
on-hook
or off-hook. Transformer A3T1 provides dc isolation between the
phone
system
and
the
modem
. The metal-oxide varistor
A3RV1
provides voltage-surge protection.
A3R4
and
A3C9 provide
an
ac
path
to allow for ring detection.
A3CR7-A3CRll,
A3R5,
and
A3U18
combine to provide
both
a ring detect function
and
a valid
phone
line detect function. When
the
-
phone
is on-hook (no dc current flowing),
an
ac signal with sufficient amplitude (such as a ring signal)
will cause the opto-isolator A3U18 to activate, pulling the MRING signal low, indicating that a ring
signal
is
being received. When the modem is off-hook
and
a valid phone line is connected, dc current
will
flow,
forcing U18 to be always on
and
MRING to be a constant
low,
indicating
that
a valid
phone
line is present.
A3RS
and
A3CRll
combine to limit the amount
of
current which flows through
A3U18 to a
'safe'
level.
5.14
Clock/Ready
Circuit
The
clock/ready
circuit consists
of
an
82C84 clock
IC
(A2U6), a 74HC393 counter IC (A2U2), a
NAND
logic gate (A2U14, pins 11, 12,
and
13),
and
a
l6-MHz
crystal (A2Yl).
Note: This circuit does
not
provide the real-time clock; the PPU performs that function.
The clock/ready circuit generates several clock frequencies.
A S.33-MHz, 33%
duty
cycle clock is fed from A2U6, pin 8 to
CLK
(pin
19
of
the
CPU),
and
to the
'wait
state" counter A2U2, pin 1. A 2.67-MHz,
SO%
duty
cycle clock is fed from PCLK (A2U6 pin 2)
to the MCLK (pins 23
of
the two
ILKS
multi-controllers A2U16
and
A2U18). A l6-MHz,
SO%
duty
cycle clock is sent from the 82C84A oscillator output (A2U6, pin 12) to a binary counter at A2U2, pin
13. This clock is
then
divided
down
to 2 MHz, 50%
duty
cycle
and
fed to
TSCLK
of
the HP-IL
interface
IC
(A2U1S, pin 22).
The LCDC
II
controller A2UlO has its
own
S-MHz oscillator (with internal decoupling).
The 680S
PPU
(A2U17) contains a I-MHz crystal
and
an
on-board oscillator
that
always operates,
even
when
the computer is asleep.
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