Portable
PLUS
Computer
Functional
Description
5·23
5.15.12
ii-kHz
Oscillator
A2US3, a quad-NOR integrated circuit, forms the heart of this oscillator. On-off control of the oscil-
lator is provided by A2Q78.
If
SLEEP is at logic 1 (sleep mode) or RS2320N is at logic 0, A2Q78 is
guaranteed to be off. This allows A2R114 to pull
up
input
pins 2
and
13
of A2US3. Output pins 3
and
11
are therefore at logic
O.
Input pins 1, 12,
8,
and
6 are driven to logic o. A2C63 is discharged so that
both terminals are at
OV.
Output pins
10
and
4 are at logic 1, a voltage of
VBAT.
This turns on A2Q80
and
turns off A2Q79. The voltage doublers have
OV
as their input voltage, so they transfer no power
to the RS-232-C driver chip.
To
turn
on
the oscillator, SLEEP is set to logic 0 (awake mode)
and
RS2320N
is
set to logic
1.
A2Q78
turns on
and
sets input pins 2
and
13
to logic
O.
This allows the pin 3
and
pin
11
NOR-gates to
operate as inverters,
and
they start to oscillate. Each time that pin
11
switches to logic 1, A2C63 ac
couples the transition through to input pin
1.
Pin
11
is logically the double inversion of pin 1, so there
is a positive feedback
situation-pin
11
stays at logic
1.
Eventually capacitor A2C63 discharges
through A2R116,
and
pin 1 becomes a logic O. This causes pin
11
to
switch to logic
o.
Again, A2C63
provides ac coupled positive feedback, so pin
11
stays at
logiC
0 for a time. Eventually A2C63 is
charged through A2R116; pin 1 becomes a
logiC
1
and
pin
11
switches back to logic
1.
The period of
the
oscillator is determined by the charge
and
discharge times of A2C63.
A2RllS
is required in the circuit to limit the input current of pin
1.
The voltage transistions that are
coupled through A2C63 go above
VBAT
and
below ground, and A2R11S prevents the internal input
protection diodes of pin 1 from being over-stressed. The pin
10
and
pin 4 NOR-gates buffer the pin
11
output
and
drive the gates of A2Q79
and
A2Q80. A2Q79
and
A2Q80 in turn act as
an
inverter buffer
and
drive the voltage doublers.
5.16
System
ROM and Built-In RAM
On
the memory PCA, AIU8 through A1UlS and A1U19 through AIU26 are
16
32K-byte
RAM
ICs
(RAM blocks
0 through
3)
. AIU16
and
AIU27 are 128K-byte ROM ICs. A1U30
is
the 8K-byte con-
figuration
EPROM, which is described
in
section S.17. The ROM
and
EPROM ICs are mounted in
sockets.
RAM can have 16-bit
and
8-bit accesses.
If
LBHE* is
low,
an
upper-byte
RAM
IC
is selected.
If
LAO
is
low (even address), a lower-byte
RAM
IC
is
selected.
If
both conditions exist, a 16-bit word access is
performed.
ROM is always accessed
in
16-bit words, even though the CPU may need only one byte.
The
BALE
signal pulses high at the start
of
each CPU cycle, turning off all
RAM
and
ROM select
signals from
AIU3, AIU4
and
AIUS while the address bus stabilizes.
To Next Page
Loading...
