Portable
PLUS
Computer
Functional
Description
5·5
The PPU
has
six open drain inputs
(PCO,
PCl,
PC3, PC4, PCS,
and
PC7). Every 128 ms it pulls
PA3
(pin
8)
low, waits 56
IlS
(for the input lines to stabilize),
and
then takes its sample.
PA3
then goes high
to
shut
off
A2Ql
and
save battery power.
5.4
Address/Control Circuit
The address/control circuit connects the CPU to the
I/O
and
memory circuits located
on
the address
and
data buses. This circuit consists of latches A2U3, A2U4,
and
A2US; transceivers
A2Ull
and
A2U12; decoders A2U7, A2U9,
and
A2U13.
The address/control circuit interfaces the multiplexed
CPU address/data bus (ADO-ADlS) with the
latched address bus
(LAO-LAlS)
and
the latched data bus (DO-DIS). These latched buses are standard
(non·multiplexed) buses. All addresses placed
on
the latched address bus come from the CPU.
The two latches transfer address information from the CPU address/data bus to the latched bus.
When
ALE
is high, the signals are transferred to the CPU circuits.
On
the falling edge of
ALE,
the
address signals are latched at the output.
The two transceivers buffer data between the
CPU address/data bus
and
the latched data bus. The
direction of transfer is set by the
DT
/R*
signal from the CPU buffer (high indicates transfer from the
CPU). A low
DEN*
signal from the CPU bus select circuit enables the transceivers. Data
is
transferred
when
a write or read signal activates the selected
Ie.
Decoder A2U7 selects individual circuits to transfer data
on
the latched data bus. When the
ALE
signal
is low, this 3-to-8 decoder uses address lines
AS,
A6,
and
A7 to select the HP-IL interface LB3CS*,
the
PPU circuit PPUCS*, the keyboard interface LKSCS*, or the
LCD
interface registers LCDRCS*.
When signals
ALE
and
LM/IO*
are
low,
decoder A2UI3 uses address lines
A14
and
AIS to select the
configuration
EPROM (27C64CS*) to transfer data
on
the latched data bus.
Buffer
A2U8 provides the interrupt byte to the CPU. When the CPU sets INTA* low, the buffer pulls
data bus lines
DO
thru D7 high. The CPU then reads the interrupt byte (and uses only the lower byte).
AIU4
and
AIUS are 3-to-8 decoders that select one of eight 64K-byte pairs of
RAM
ICs.
RAM
is
divided into four 128K-byte blocks
(0,
1,
2,
and
3). Decoder AIU3 provides select signals for ROM
and
display
RAM
accesses. Buffers AIU6 amd
AIU7
reduce capacitive loading
on
the address bus to
the
RAM
ICs. Buffer
AIUI
buffers CPU control signals for the memory PCA
and
plug-in devices.
5.5
Keyboard
Interface
Multicontroller A2U16
and
the SIP resistors A2RI2, A2R13,
and
A2R14 provide
the
electrical interface
to the keyboard. The keyboard assembly contains the 76 key mechanisms, but
no
electronic compo-
nents. Hardware supplies the key locations,
and
software maps these locations into unique key codes.
The keyboard
is
organized into an eight by nine matrix with three additional function-modifier keys.
A matrix key connects a row to a column. The matrix uses the following precharge/discharge scheme:
columns
precharge
high,
rows
precharge
low
.
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