Portable
PLUS
Computer
Functional
Description
5-13
The computer's
bus
cycle length varies
depending
on
the address
of
the device being accessed. This is
provided by the CPU's
READY
input.
The lower 512K bytes
of
memory space
run
with
no
wait states,
and
cycle times
of
748 ns. There is
no
way
to extend cycle times
in
this region. The
upper
512K bytes of memory space
and
all
I/O
cycles
operate
with
a minimum of
one
wait state
and
a minimum cycle time
of
935 ns. These cycles can be
extended
by
pulling the CPU's READY line low,
and
are extended indefinitely until
the
READY
signal
goes high.
5.15
Power
Supply
The
power supply contains four circuits
that
operate
under
control of the PPU. These circuits perform
the following functions:
• Provide the regulated supply voltages (VccDS
and
VccS).
• Recharge the battery (and indicate state of charge).
• Provide the selectable LCD supply voltage (VLCD).
• Provide supply voltages for the RS-232-C serial interface.
5.15.1
vee Voltage
Regulator
The
VCC regulator has two supply outputs: VccDS
and
VccS. Its input (provided by the battery volt-
age
VBAT)
is constrained to
be
in
the range 5.6V to
8V.
SLEEP is the main control
input
to the VCC
regulator provided by the PPU. SLEEP affects the two supply output voltages.
When
SLEEP is at logic 1, the computer is in sleep mode (which appears as
'off'
to the user). In this
. mode,
the
product draws the least battery
current-less
than
300 /lA. Only the circuitry required to
maintain clock operation
and
the user's data is powered. VccDS
is
regulated to 3.25 Vdc, logic 1 levels
are roughly 3.25V,
and
logic 0 levels are roughly
OV.
The PPU, its associated circuitry,
and
the mem-
ory circuitry is powered
by
VccDS, so these functions are maintained in sleep mode.
VccS
powers
circuitry
that
does
not
need
to operate while
in
sleep mode, so
VccS
becomes a high impedance node
and
eventually discharges to
OV
when
SLEEP is
at
logic 1.
When
SLEEP is set to logic 0 by the PPU, the computer is in awake mode ('on" to the user). VccDS
and
VccS are regulated to 5 Vdc ± 5% with
up
to 300
rnA
total load
on
both supplies. Logic 1 levels
are roughly
5V,
and
logic 0 levels are roughly
OV.
PLUGINl*
and
PLUGIN2* are the two other inputs provided to the VCC regulator. These inputs are
grounded
when
cards are plugged into slot 1
or
slot 2, respectively. If either of these lines becomes
ungrounded
while
the
computer is awake, the regulator enters a
shut-down
state-VccDS
is driven to
OV
and
VccS becomes high impedance (turns off). All processor activity, clock operation,
and
memory
retention cease. The reason for this state is to prevent latch-up of the CMOS digital circuitry in the
event
that
the
user removes a card while it is being accessed. The VCC regulator stays
in
this state
until
both
PLUGINl*
and
PLUGIN2* are grounded.
If
PLUGINl*
or
PLUGIN2* becomes
un-
grounded
while the computer is
in
sleep mode, the VCC regulator operates normally
and
maintains
sleep mode.
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