5-6
Functional
Description
Portable
PLUS
Computer
The 1
LK5
(A2U16) row drivers are tristated,
and
the columns are precharged. Bleeder resistor A2R14
keeps the floating rows
at
ground potential
and
the rows are read
at
this time.
If
a
row
goes high, a
key has been pressed. Transceiver (A2U16)
then
switches to tristate the column precharge drivers,
turn
on
its row drivers,
and
sample the column lines. Resistors A2R12
and
R13
keep floating columns at
the positive supply potential.
If
a column goes low, then a key has been pressed. A closed key will
cause a square
wave
on
the connected row
and
column (high pulse width
is
12 /Lsec nominal; low
pulse width is 11.25
/LS
nominal).
When
no keys are pressed, all columns are at the positive supply
potential,
and
all rows are at ground potential.
The three function-modifier keys each have their
own
pull-
up
resistor to the
+5V
power supply. A
closed key pulls its resistor to ground.
5.6
Keyboard
Assembly
The keyboard assembly contains 76 full-travel, 3J4-throw keys; it contains no active circuitry.
When
a
key is pressed, the corresponding row
and
column lines are connected; this
is
detected by the key-
board interface circuit. Connections between the keyboard
and
motherboard PCA are made via the
26-pin connector A2J5. (Refer to the schematic diagram in figure 12-5 for the A2J5 connector
pin
assignments.)
5.7
Liquid-Crystal (LCD)
Interface
The LCDC
II
hybrid (A2U10) functions as a single chip interface
to
the liquid-crystal display (LCD).
The 48-pin hybrid contains two 8K-by-8 static RAMs
and
the LCD controller.
The LCDC
II
is
connected
to
the CPU
address/data
bus
and
operates at 5 MHz.
It
latches the CPU's
address
on
the falling edge of
ALE
and
is
accessed only
when
one of its three chip-selects goes active
(low).
The
LCDMCS* line signals
an
access to the display
RAM,
and
the LCDRCS* signals
an
access
to the LCDC
II
's internal registers. The third chip-select line signals a CPU access to the PPU's byte-
wide
port
(I/O
address 0060 hex).
The
LCDC
II
uses its
open
drain
READY
output
to control CPU accesses: access cycle times vary with
synchronization to its internal clock phases
and
with display refresh accesses.
The LCDC
II
control registers
and
the display RAM remain powered
when
the computer is asleep.
The LCD connects to the motherboard PCA via 12-pin connector
A2J9
. (Refer to the schematic
dia-
gram in figure 12-4 for pin assignments.)
5.8
Liquid-Crystal Display
A 480-by-200 dot liquid-crystal display provides the computer's visual output. Alpha
output
is dis-
played as
25
lines of 80 characters. Graphics
output
is
displayed as a 480-by-200
dot
pattern.
Connections between the LCD module
and
the motherboard PCA are made via 12-
pin
connector
A2J9
. (Refer to the schematic diagram in figure 12-4 for the A2J9 connector pin assignments.)
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