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General| Brand | Intel |
|---|---|
| Model | Agilex |
| Category | Microcontrollers |
| Language | English |
Provides a general overview of the device's configuration capabilities and security features.
Details the specific cables used for programming and debugging the device.
Illustrates the critical timing signals and states during configuration and reconfiguration processes.
Visually represents the sequence of states during device configuration.
Explains the IP required to hold designs in reset until configuration is complete.
Outlines clock requirements for specific hardware blocks.
Describes the various pins used for configuration and their functions.
Details the specific assignments of SDM I/O pins for different configuration schemes.
Explains how MSEL pins are used to select the configuration scheme.
Covers configuration pins that are not dedicated and can be assigned optionally.
Provides steps to assign optional configuration pins using software.
Describes how to enable and configure dual-purpose pins for specific functions.
Details electrical characteristics of configuration pins.
Describes the fastest configuration scheme using Avalon Streaming.
Details the components and file types for Avalon-ST configuration.
Steps to enable the Avalon-ST scheme in software.
Explains the flow control signal for Avalon-ST.
Offers troubleshooting tips for Avalon-ST configuration issues.
Describes the Active Serial configuration scheme.
Details hardware components and file types for AS configuration.
Shows connections for single-device AS configuration.
Covers timing parameters for AS configuration, including serial output and input diagrams.
Offers troubleshooting tips for AS configuration.
Describes configuration using SD memory cards or MMC.
Explains the simplest device configuration scheme using JTAG.
Details hardware components and file types for JTAG configuration.
Explains how to configure a single device in a JTAG chain.
Provides troubleshooting tips for JTAG configuration.
Details the PFL II IP core for Avalon-ST configuration.
Provides an overview of the RSU functionality and its advantages.
Defines key terms related to RSU.
Explains how RSU works with the AS configuration scheme.
Describes the types of images used in RSU.
Illustrates the sequence of operations for RSU.
Details how to recover from corrupted images during RSU.
Provides guidelines for implementing RSU without HPS.
Describes the commands and responses used for RSU operations.
Lists and describes the specific commands for RSU.
Describes the layout of Quad SPI flash memory for RSU.
Provides a high-level view of the flash layout.
Describes the flash layout for non-RSU scenarios.
Explains the flash layout from the SDM's perspective.
Explains the flash layout from the user's perspective.
Provides a detailed breakdown of the Quad SPI flash layout.
Details the layout of RSU flash sub-partitions.
Explains the structure of the configuration pointer block.
Guides on creating RSU image files.
Steps to generate the initial RSU image.
Steps to generate an application image.
Steps to generate a factory update image.
Details programming the flash with the initial RSU image.
Explains how to reconfigure the device with different images.
Steps to add a new application image.
Covers the security features of Intel Agilex devices.
Explains the CvP configuration scheme.
Describes the process of reconfiguring parts of the FPGA.
A checklist to help identify and resolve configuration issues.
Provides an overview of the device's configuration architecture.
Explains differences in configuration file formats.
Explains the behavior of configuration pins and how to troubleshoot them.
Details the function and behavior of the nCONFIG pin.
Details the function and behavior of the nSTATUS pin.
Describes the CONF_DONE and INIT_DONE signals.
Lists user guides for different IP core versions.
Details the changes made in different document versions.
