The SDM drives Intel Agilex device configuration.
Initial Configuration Timing
The first section of the figure shows the expected timing for initial configuration after a normal power-on reset. Initially, the
application logic drives the nCONFIG signal low. Under normal conditions nSTATUS follows nCONFIG because nSTATUS
reflects the current configuration state. nCONFIG must only change when it has the same value as nSTATUS.
When an error occurs, nSTATUS pulses low for approximately 1 ms and asserts high when the device is ready to accept
reconfiguration.
The numbers in the Initial Configuration part of the timing diagram mark the following events:
1.
The SDM boots up and samples the MSEL signals to determine the specified FPGA configuration scheme. The SDM does
not sample the MSEL pins again until the next power cycle.
2.
With the nCONFIG signal low, the SDM enters Idle mode after booting.
Note:
For Avalon-ST x16 and x|32 configuration schemes the host must drive nCONFIG low until it samples nSTATUS low.
If the host fails to drive nCONFIG low until it samples nSTATUS low there is a chance that configuration may fail.
3.
When the external host drives nCONFIG signal high, the SDM initiates configuration. The SDM drives the nSTATUS signal
high, signaling the beginning of FPGA configuration. The SDM receives the configuration bitstream on the interface that
the MSEL bus specified in Step 1 The diagram shows AVST_READY and AVST_VALID continuously high. It is possible for
AVST_READY to deassert which would require AVST_VALID to deassert within six cycles.
4.
The SDM drives the CONF_DONE signal high, indicating the SDM received the bitstream successfully.
5.
When the Intel Agilex device asserts INIT_DONE to indicate the FPGA has entered user mode. GPIO pins exit the high
impedance state. The time between the assertion of CONF_DONE and INIT_DONE is variable. For FPGA First configuration,
INIT_DONE asserts after initialization of the FPGA fabric, including registers and state machines. For HPS first
configuration, the HPS application controls the time between CONF_DONE and INIT_DONE. INIT_DONE does not assert
until after the software running on the HPS such as U-Boot or the operating system (OS) initiates the configuration, the
FPGA configures and enters user mode..
The entire device does not enter user mode simultaneously. Intel requires you to include the Reset Release Intel FPGA IP
on page 23 in your design. Use the nINIT_DONE output of the Reset Release Intel FPGA IP to hold your application logic
in the reset state until the entire FPGA fabric is in user mode. Failure to include this IP in your design may result in
intermittent application logic failures.
2. Intel Agilex Configuration Details
UG-20205 | 2019.10.09
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