Intel Agilex User Manual

Reconfiguration Timing
The second event the timing diagram illustrates the Intel Agilex device reconfiguration. If you change the MSEL setting after
power-on, you must power-cycle the Intel Agilex. Power cycling forces the SDM to sample the MSEL pins before reconfiguring
the device.
The numbers in the Reconfiguration part of the timing diagram mark the following events:
1.
The external host drives nCONFIG signal low.
2. The SDM initiates device cleaning.
3.
The SDM drives the nSTATUS signal low when device cleaning is complete.
4.
The external host drives the nCONFIG signal high to initiate reconfiguration.
5.
The SDM drives the nSTATUS signal high signaling the device is ready for reconfiguration and starts to reconfigure.
Configuration Error
The numbers in the Configuration Error part of the timing diagram mark the following events:
1.
The SDM drives nSTATUS signal low for 1 ms -0.5 ms/+9.5 ms to indicate a configuration error. The Intel Agilex
device does not assert CONF_DONE indicating that configuration did not complete successfully.
2.
The SDM enters the error state. During the error state, nCONFIG should be in the high state. The application must drive
nCONFIG from high to low and then from low to high to restart configuration.
3.
The SDM enters the idle state. The external host deasserts nCONFIG. The device is ready for reconfiguration by driving a
low to high transition on nCONFIG. You can also power cycle the device by following the device power down sequence.
Note:
The nCONFIG signal can only change levels when it has the same value as nSTATUS. This restriction means that
when nSTATUS = 1, nCONFIG can transition from 1 to 0. When nSTATUS = 0, nCONFIG can transition from 0 to 1.
Apart from error reporting, nSTATUS only changes to follow nCONFIG.
Power Supply Status
The power-on reset (POR) holds the Intel Agilex device in the reset state until the power supply outputs are within the
recommended operating range. t
RAMP
defines the maximum power supply ramp time. If POR does not meet the t
RAMP
time,
the Intel Agilex device I/O pins and programming registers remain tri-stated.
For more information about POR refer to the Intel Agilex Power Management User Guide. For more information about t
RAMP
refer to the Intel Agilex datasheet.
2. Intel Agilex Configuration Details
UG-20205 | 2019.10.09
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Configuration User Guide
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English