Document Version Intel Quartus
Prime Version
Changes
•
Removed vector for Power_Supply_Status in the Configuration, Reconfiguration, and Error Timing Diagram figure.
•
Corrected the Intel Agilex FPGA Configuration Flow diagram. The transition between FPGA Config* and User Mode
should say INIT_DONE = HIGH.
•
Corrected the following statement in the Debugging Guidelines for the JTAG Configuration Scheme topic: An nSTATUS
falling edge terminates any JTAG access and the device reverts to the MSEL-specified boot source. nSTATUS must be
stable during JTAG configuration.. In both sentence, nSTATUS should be nCONFIG.
•
Removed pin assignments for CVP_CONFDONE for the Avalon-ST in the Available SDM I/O Pin Assignments for
Configuration Signals that Do Not Use Dedicated SDM I/O Pins table. CvP does not the support Avalon-ST x8 configuration
scheme in Intel Agilex devices.
2019.04.03
19.1 Removed references to documents that are not yet available.
2019.04.02 19.1 Initial Release
8. Document Revision History for the Intel Agilex Configuration User Guide
UG-20205 | 2019.10.09
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