Intel Agilex User Manual

Document Version Intel Quartus
Prime Version
Changes
2019.07.01 19.2 Made the following changes:
•
Corrected Step 3 in the Initial Configuration Timing description. The step should say, with nConfig low, the SDM enters
Idle mode after booting.
• Added note that designs using Avalon-ST x16 and x32 configuration scheme may need to include a voltage translator
between the FPGA and external host because some signals, to accommodate the GPIO pins that only support the 1.2 V
I/O standard and the SDM I/O pins require a 1.8 V power supply.
• Created separate topic covering partial configuration.
• Revised and reorganized all topics covering configuration pin assignments:
—
Clarified the behavior of the MSEL pins in AS x4 mode.
— Added information about the SDM_IO pin states during power-on and after device cleaning to the Intel Agilex
Configuration Pins topic.
— Created separate topics covering partial configuration and SmartVID signals.
• Made the following changes to the RSU chapter:
— Added the following topics:
• RSU Glossary
• Standard (non-RSU) Flash Layout
• RSU Flash Layout – SDM Perspective
• RSU Flash Layout – Your Perspective
• Detailed Quad SPI Flash Layout
• Sub-partitions Layout
• Sub-Partition Table Layout
• CMF Pointer Block Layout
• Modifying the List of Application Images
• Application Image Layout
• Command Sequence To Perform Quad SPI Operations
— The static firmware has been replaced by decision CMF.
— The update image now includes the factory image, the decision CMF and the decision CMF data.
—
The QSPI_ERASE command is now 4 KB aligned. The number of words to erase must be a multiple of 1024.
—
Added definitions of major and minor error codes for RSU_STATUS and CONFIG_STATUS.
• Added footnote explaining that before you can use CvP you must configure either the periphery image or the full image via
the AS configuration scheme. Then, you can configure the core image using CvP.
• Added recommendation to use the Analog Devices LTM4677 device to regulate the PMBus for SmartVID devices. You set
this parameter here: Device ➤ Device and Pin Options ➤ Power Management & VID ➤ Slave device type.
• Corrected maximum speed and data rate in the Intel Agilex Configuration Data Width, Clock Rates, and Data Rates table.
The Max Clock Rate is 33 MHz. The Max Data Rate is 33 Mbps.
• Added the eSRAM clocks to the list of free-running clocks that must be stable before configuration begins.
• The Reset Release Intel Agilex FPGA IP is now available for Intel Agilex devices.
continued...
8. Document Revision History for the Intel Agilex Configuration User Guide
UG-20205 | 2019.10.09
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Configuration User Guide
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English