Intel Arria 10 FPGA - 6.10.1.1. DDR3 L

6.10.1. External Memory Interface
Related Information
Arria 10 FPGA and SoC External Memory Resources
6.10.1.1. DDR3L
The DDR3L x 72 SDRAM (DDR3 Low Voltage)
Figure 37. DDR3 Block Diagram
VDD/VDDQ
EMIF
H
I
L
O
Connector
DDR3L x 72
DDR3 SDRAM
U1
DDR3 SDRAM
U2
DDR3 SDRAM
U3
DDR3 SDRAM
U4
DDR3 SDRAM
U5
Byte 8
Byte 6-7
Byte 4-5
Byte 2-3
Byte 0-1
DQ/DQS/DM
Addr/Ctrl/clk
Addr/Ctrl/clk
3.3 V/2.5 V
VTT Regulator
DDR3L_VTT
DDR3L_VREF
MT41K512M16TNA-107
MT41K512M16TNA-107
MT41K512M16TNA-107
MT41K512M16TNA-107
MT41K512M16TNA-107
6. Board Components
683526 | 2023.07.12
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10 FPGA Development Kit User Guide
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