Intel Arria 10 FPGA User Manual

4.4.9. The DDR3 Tab
This tab allows you to read and write DDR3 memory on your board.
Figure 24. The DDR3 Tab
Control Description
Start Initiates DDR3 memory transaction performance analysis.
Stop Terminates transaction performance analysis.
Performance Indicators These controls display current transaction performance analysis
information collected since you last clicked Start:
• Write, Read, and Total performance bars—Show the percentage of
maximum theoretical data rate that the requested transactions are able
to achieve.
• Write (MBps), Read (MBps), and Total (MBps)—Show the number
of bytes of data analyzed per second.
• Data bus: 72 bits (8 bits ECC) wide and the frequency is 1066 MHz
double data rate. 2133 Megabits per second (Mbps) per pin. Equating
to a theoretical maximum bandwidth of 136512 Mbps or 17064 MBps.
Error Control This control displays data errors detected during analysis and allows you to
insert errors:
continued...
4. Board Test System
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10 FPGA Development Kit User Guide
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Intel Arria 10 FPGA Specifications

General

Brand	Intel
Model	Arria 10 FPGA
Category	Microcontrollers
Language	English