Intel Arria 10 FPGA User Manual

4.4.6. The PCIe Tab
This tab allows you to run a PCIe loopback test on your board. You can also load the
design and use an oscilloscope to measure an eye diagram of the PCIe transmit
signals.
Figure 21. The PCIe Tab
Control Description
Status Displays the following status information during a loopback test:
PLL lock—Shows the PLL locked or unlocked state.
Pattern sync—Shows the pattern synced or not synced state. The pattern
is considered synced when the start of the data sequence is detected.
continued...
4. Board Test System
683526 | 2023.07.12
Intel
®
Arria
®
10 FPGA Development Kit User Guide
Send Feedback
34

Intel Arria 10 FPGA Specifications

General

Brand	Intel
Model	Arria 10 FPGA
Category	Microcontrollers
Language	English